DSP Code and Timing Patterns: Difference between revisions

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[[Media:Whole_array_line_1.ps|Whole Array Line 1 Timing Pattern]]
[[Media:Whole_array_line_1.ps|Whole Array Line 1 Timing Pattern]]


[[Whole_Frame_tim.asm|Whole_Frame_tim.asm]]
[[Media:Whole_Frame_tim.asm|Whole_Frame_tim.asm]]

Revision as of 18:29, 1 October 2009

host

Multiple Reads per Reset Timing Pattern

Multiple Reads per Reset Timing Pattern

pci.Iod

pci.rom

pci.s

pciboot.asm

PICNIC.setup

PICNIC.waveforms

README file distributed by Leach

rom

Subarray Frame Start Timing Pattern

Subarray Frame Timing Pattern

Subarray Line 1 Timing Pattern

Subarray Line 1 Timing Pattern

Subarray Line 2 Timing Pattern

Subarray Line 2 Timing Pattern

Subarray Multiple Reads Timing Pattern

Subarray Multiple Reads Timing Pattern

SXMIT Timing Pattern

TAR file with all DSP code

tim

tim.asm

tim.Iod

tim.rom

tim.s

timboot.asm

timCCD.asm

timhdr.asm

timIRmisc.asm

timrom

timrom.asm

Whole Array Line 1 Timing Pattern

Whole Array Line 1 Timing Pattern

Whole_Frame_tim.asm

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