; Miscellaneous definitions VIDEO EQU $000000 ; Video board select = 0 for first A/D board with biases CLK2 EQU $002000 ; Clock board select = 2 CLK3 EQU $003000 ; Clock board select = 3 DELAY EQU $050000 ; Delay for clocking operations ; (20 ns unit, 160 if MSB set) VP_DLY EQU $100000 ; Video delay time SXMIT EQU $00F0C0 ; Series transmit A/D channels #0 to 3 ; Clock voltage definitions CLK_HIGH EQU $CC0 ; ~+4V, assuming +VREF = +2.5 CLK_LOW EQU $0F4 ; ~+.30V, assuming -VREF = 0.0 ; Logic analyzer values ;CLK_HIGH EQU $a00 ;CLK_LOW EQU $7E0 ; Table of offset values begins at Y:$10 ; DAC settings for the video offsets DC_BIASES DC END_DC_BIASES-DC_BIASES-1 OFF_0 DC $0c0000 ; Input offset board #0, channel A OFF_1 DC $0c4000 ; Input offset board #0, channel B OFF_2 DC $1c0000 ; Input offset board #1, channel A OFF_3 DC $1c4000 ; Input offset board #1, channel B ; DAC settings to generate DC bias voltages for the PICNIC array VOFFSET DC $0c8bd4 ; pin #1 = preamp offset = +3.7 volts VRESET DC $0cc195 ; pin #2 = reset = +0.5 volts VD DC $0d0fff ; pin #3 = analog power = +5.0 volts ICTL DC $0d4bd4 ; pin #4 = current control = +3.7 volts VDD DC $0d8ccb ; pin #5 = digital power = +4.0 volts VUNUSED DC $0dc000 ; pin #6 = unused to 0V END_DC_BIASES ; Zero out the DC biases during the power-on sequence ZERO_BIASES DC END_ZERO_BIASES-ZERO_BIASES-1 DC $0c8000 ; Pin #1, board #0 DC $0cc000 ; Pin #2 DC $0d0000 ; Pin #3 DC $0d4000 ; Pin #4 DC $0d8000 ; Pin #5 DC $0dc000 ; Pin #6 DC $1c8000 ; Pin #1, board #1 DC $1cc000 ; Pin #2 DC $1d0000 ; Pin #3 DC $1d4000 ; Pin #4 DC $1d8000 ; Pin #5 DC $1dc000 ; Pin #6 END_ZERO_BIASES ; Initialize all DACs, starting with the clock driver ones DACS DC END_DACS-DACS-1 DC (CLK2<<8)+(0<<14)+CLK_HIGH ; Pin #1, RESET DC (CLK2<<8)+(1<<14)+CLK_LOW DC (CLK2<<8)+(2<<14)+CLK_HIGH ; Pin #2, LINE DC (CLK2<<8)+(3<<14)+CLK_LOW DC (CLK2<<8)+(4<<14)+CLK_HIGH ; Pin #3, LSYNC DC (CLK2<<8)+(5<<14)+CLK_LOW DC (CLK2<<8)+(6<<14)+CLK_HIGH ; Pin #4, FSYNC DC (CLK2<<8)+(7<<14)+CLK_LOW DC (CLK2<<8)+(10<<14)+CLK_HIGH ; Pin #6, READ DC (CLK2<<8)+(11<<14)+CLK_LOW DC (CLK2<<8)+(24<<14)+CLK_HIGH ; Pin #13, PIXEL DC (CLK2<<8)+(25<<14)+CLK_LOW END_DACS ; Define switch state bits for the first group of 12 clocks = CLK2 H_RESET EQU 1 ; Pin #1 L_RESET EQU 0 H_LINE EQU 2 ; Pin #2 L_LINE EQU 0 H_LSYNC EQU 4 ; Pin #3 L_LSYNC EQU 0 H_FSYNC EQU 8 ; Pin #4 L_FSYNC EQU 0 H_READ EQU $20 ; Pin #6 L_READ EQU 0 ; Define switch state bits for the second group of 12 clocks = CLK3 H_PIXEL EQU 1 ; Pin #13 L_PIXEL EQU 0 ;SXMIT EQU $00F0C0 ; Transmit A/Ds = 0 to 3 ;SXMIT EQU $00F000 ; Transmit A/D = 0 ;SXMIT EQU $00F041 ; Transmit A/D = 1 ;SXMIT EQU $00F082 ; Transmit A/D = 2 ;SXMIT EQU $00F0C3 ; Transmit A/D = 3 ; Symbolic definitions ; DC CLK2+DELAY+L_FSYNC+L_LSYNC+L_LINE+L_READ+L_RESET ; DC CLK3+DELAY+L_PIXEL ; Turn READ ON for readout and reset READ_ON DC END_READ_ON-READ_ON-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET END_READ_ON ; Turn READ OFF during exposure READ_OFF DC END_READ_OFF-READ_OFF-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+L_READ+L_RESET END_READ_OFF ; Initialize the frame for readout, including shift register (slow row scanner) INIT_FRAME DC END_INIT_FRAME-INIT_FRAME-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+L_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+L_FSYNC+L_LSYNC+L_LINE+H_READ+L_RESET END_INIT_FRAME SHIFT_RESET_ODD_ROW DC END_SHIFT_RESET_ODD_ROW-SHIFT_RESET_ODD_ROW-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+L_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+H_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+L_RESET END_SHIFT_RESET_ODD_ROW SHIFT_RESET_EVEN_ROW DC END_SHIFT_RESET_EVEN_ROW-SHIFT_RESET_EVEN_ROW-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+L_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+H_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET END_SHIFT_RESET_EVEN_ROW SHIFT_EVEN_ROW DC END_SHIFT_EVEN_ROW-SHIFT_EVEN_ROW-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+L_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+L_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET ; DC CLK3+DELAY+H_PIXEL END_SHIFT_EVEN_ROW SHIFT_ODD_ROW DC END_SHIFT_ODD_ROW-SHIFT_ODD_ROW-1 DC CLK3+DELAY+L_PIXEL DC CLK2+DELAY+H_FSYNC+L_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+L_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+L_LINE+H_READ+L_RESET DC CLK2+DELAY+H_FSYNC+H_LSYNC+H_LINE+H_READ+L_RESET ; DC CLK3+DELAY+H_PIXEL END_SHIFT_ODD_ROW SHIFT_READ_PIXELS DC END_SHIFT_READ_PIXELS-SHIFT_READ_PIXELS-1 DC CLK3+DELAY+H_PIXEL DC $400000 ; A/D sample DC $010033 ; Start A/D conversion SXMIT0 DC SXMIT ; Series transmit four pixels' data DC 0 ; Return SXMIT to zero DC CLK3+DELAY+L_PIXEL DC $400000 ; A/D sample DC $010033 ; Start A/D conversion SXMIT1 DC SXMIT ; Series transmit four pixels' data DC 0 ; Return SXMIT to zero END_SHIFT_READ_PIXELS ; Advance the row shift register as quickly as possible, 240 nsec/pixel SHIFT_PIXELS DC END_SHIFT_PIXELS-SHIFT_PIXELS-1 DC CLK3+DELAY+H_PIXEL DC CLK3+DELAY+L_PIXEL END_SHIFT_PIXELS READ_PIXEL DC END_READ_PIXEL-READ_PIXEL-1 DC $140000 ; A/D sample DC $010033 ; Start A/D conversion SXMIT00 DC SXMIT ; Series transmit four pixels' data DC 0 ; Return SXMIT to zero END_READ_PIXEL SXMIT_EIGHT_PIXELS DC END_SXMIT_EIGHT_PIXELS-SXMIT_EIGHT_PIXELS-1 DC DELAY+$000033 DC VP_DLY ; A/D sample DC $000033 ; Start A/D conversion SXMIT2 DC SXMIT ; Series transmit four pixels' data DC DELAY+$000033 DC VP_DLY ; A/D sample DC $000033 ; Start A/D conversion SXMIT3 DC SXMIT ; Series transmit four pixels' data DC 0 ; Return SXMIT to zero END_SXMIT_EIGHT_PIXELS