DSP Code and Timing Patterns: Difference between revisions

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[[Media:Subarray_line_1.pdf|Subarray Line 1 Timing Pattern]]
[[Media:Subarray_line_1.pdf|Subarray Line 1 Timing Pattern]]
[[Media:Subarray_line_2.ps|Subarray Line 2 Timing Pattern]]
[[Media:Subarray_line_2.pdf|Subarray Line 2 Timing Pattern]]
[[Media:Subarray_multiple_reads_1.ps|Subarray Multiple Reads Timing Pattern]]
[[Media:Subarray_multiple_reads_1.pdf|Subarray Multiple Reads Timing Pattern]]

Revision as of 18:17, 1 October 2009

host

Multiple Reads per Reset Timing Pattern

Multiple Reads per Reset Timing Pattern

pci.Iod

pci.rom

pci.s

pciboot.asm

PICNIC.setup

PICNIC.waveforms

README file distributed by Leach

rom

Subarray Frame Start Timing Pattern

Subarray Frame Timing Pattern

Subarray Line 1 Timing Pattern

Subarray Line 1 Timing Pattern

Subarray Line 2 Timing Pattern

Subarray Line 2 Timing Pattern

Subarray Multiple Reads Timing Pattern

Subarray Multiple Reads Timing Pattern

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